1. Technical Field
The disclosure relates to an integrated circuit and an operating method for the same, and more particularly to an integrated circuit having a conductive structure and an operating method for the same.
2. Description of the Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, and arrays become very large, memory cell within an array can have characteristics that vary in a manner that affects sensing margins. In one trend to achieve high density, designers have been looking to techniques for stacking multiple levels of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies. Also, cross-point array techniques have been applied for anti-fuse memory.
In a 3D array, differences in the electrical characteristics of structures on the various levels can lead to differences in the dynamics of programming, erasing, and charge storage, including variations in threshold voltages corresponding to memory states of memory cells on the various levels. Thus, to achieve the same threshold voltages, within acceptable margins for every level, the programming and erasing processes have to be adapted to vary with the level of the target cell in some way. These variations can lead to endurance problems with the memory cells and to other complexities.
In a 3D array, access lines, such as global bit lines, arranged for use to access the various levels of the array can be laid out so that characteristics such as capacitance and inductance encountered by circuits coupled to the access lines can vary depending on the location, such as which level in the array, of the cell being accessed. For example, global bit lines typically extend to decoder circuitry used for reading and writing the memory cells. Differences among the vertical connections to the various levels, and other differences among the levels, can lead to variations in capacitance among the global bit lines. These variations in capacitance affect the global bit line voltages during read, program and erase operations, and can result in specification requirements, such as larger read margins between programmed and erased states, and slower sensing times to account for worst case capacitances.
It is therefore desirable to provide integrated circuit technologies that compensate for variations in cell characteristics within an array.